Synthesis & STA Engineer – High-Speed SerDes

The role

You will drive the planning, coordination, and execution of logic synthesis and static timing analysis for high-speed analog/mixed-signal SerDes and connectivity ASICs. This role involves end-to-end ownership of digital portions of mixed-signal SerDes PHY designs and collaboration with analog, RTL, physical design, and verification teams.

What you will do

• Perform RTL synthesis for digital controller and DSP blocks within high-speed SerDes PHY designs.
• Author, develop, and validate SDC constraints.
• Set up and manage MMMC environments.
• Drive timing closure from synthesis through sign-off.
• Define and manage I/O timing budgets and interface constraints.
• Apply advanced sign-off methodologies at TSMC 5nm/3nm and below.
• Leverage ETM/ILM libraries for hierarchical timing analysis.
• Provide timing feedback, root cause analysis, and ECO guidance.
• Manage large-scale multi-corner/multi-mode STA runs with automation.
• Generate and validate timing ECOs.

Required qualifications

• Bachelor's in Electrical Engineering or Computer Science required
• 8 or more years of experience in synthesis, timing constraints development, STA, and sign-off for high-speed mixed-signal IP in Server, Storage, Networking, or SerDes applications
• Strong proficiency in writing and debugging SDC constraints
• Expertise in STA methodology and timing closure at both block and full-chip level using Synopsys PrimeTime and/or Cadence Tempus
• Strong knowledge of synthesis, place-and-route, extraction, and equivalence checking flows in advanced nodes (5nm/3nm and below)
• Proficiency with Cadence and/or Synopsys physical design/STA toolchains
• Strong scripting ability (Tcl, Python, Perl)
• Ability to work independently with strong prioritization and a professional, customer-focused mindset

Nice to have

• Master's preferred
• Direct experience with high-speed SerDes, Ethernet PHY (112G/224G), or PCIe/CXL PHY digital controller and DSP timing challenges
• Understanding of analog/mixed-signal integration concerns
• Knowledge of ECO methodologies, DFT tools, and test coverage analysis for mixed-signal designs
• Experience working with IP vendors for both RTL and hard-macro integration
• SystemVerilog/Verilog proficiency
• Familiarity with power-aware synthesis and STA (UPF/CPF flows)
• Experience with high-speed clocking architectures and multi-rate clock domain management

Benefits

• Discretionary bonuses
• Equity incentives
• Comprehensive benefits

About the company

Astera Labs is a global leader in purpose-built connectivity solutions for AI and cloud infrastructure. The company provides rack-scale AI infrastructure through purpose-built connectivity solutions.