Principal Design Verification Engineer- SerDes/PHY IP

The role

You will own functional verification of high-speed SerDes/PHY IP. You will architect verification environments, drive coverage closure, and partner with analog/mixed-signal designers to verify multi-Gbps SerDes blocks.

What you will do

• Architect UVM-based verification environments for SerDes/PHY IP
• Define verification plans, coverage models, and sign-off criteria
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models
• Execute functional, performance, and corner-case verification
• Lead coverage analysis and closure and debug failures with designers
• Verify PHY behavior against industry specifications
• Model and validate channel behavior, link training state machines, and analog handoff scenarios
• Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models
• Mentor junior DV engineers and set technical direction

Required qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field
• 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP
• Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up
• Expert-level proficiency in SystemVerilog and UVM
• Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM)
• Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering
• Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP
• Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows
• Scripting proficiency in Python or Perl for verification automation and regression management
• Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results
• Proven ability to lead technically across a multi-disciplinary team in a fast-paced environment

Benefits

• discretionary bonus
• incentives
• benefits

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.