Senior ASIC Design Engineer

The role

This person will design digital blocks for AI infrastructure connectivity. They will own the journey from high-level definition through RTL implementation and backend support.

What you will do

• Own the journey from high-level definition through micro-architecture, coding, and debug to backend implementation support
• Tackle complex logic challenges and transform them into elegant, high-performance hardware solutions
• Serve as the point of contact for logic blocks, interacting with Architecture, Verification, and Backend teams
• Utilize industry-leading EDA tools to ensure designs are robust, scalable, and power-efficient
• Apply design techniques to meet PPA targets
• Contribute to design quality through verification and validation activities
• Participate in design methodology improvements and tool automation initiatives
• Leverage AI assistance tools and contribute to in-house automation development

Required qualifications

• Bachelor's degree in Electrical Engineering or related technical field
• 3+ years of experience in logic design at semiconductor companies
• Knowledge and experience in Verilog and/or SystemVerilog
• Excellent communication skills with ability to work effectively across teams
• Understanding of digital design principles and RTL coding best practices

Nice to have

• Master's degree in Electrical Engineering or related field
• Knowledge of DDR and PCIe protocols and implementation
• Understanding of power management techniques for low-power design
• Familiarity with Clock Domain Crossing, simulation, debugging, synthesis, and timing analysis
• Proficiency in scripting languages such as Python or Perl
• Experience with high-speed serial interface designs or connectivity protocols

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.