Staff/ Principal Chip Top Physical Design Engineer

The role

You will execute the physical design of the SoC Top level for chips that drive AI clusters. You will drive the tape-out GDS to meet signoff criteria for performance, power, and area targets.

What you will do

• Execute SoC Top-level physical design and drive full-chip convergence
• Perform Top-Level physical implementation including floor-planning, P&R, CTS, Power/Clock distribution, Power Integrity, and Timing/Physical signoff
• Work with Architecture, Design, DFT, and Product teams to achieve optimal PPA
• Participate in feasibility studies for new architectures and optimize runs
• Resolve complex signal integrity, thermal, and power challenges
• Collaborate with the Package team on Bump-map-to-Ballout design

Required qualifications

• B.Sc. or M.Sc. in Electrical Engineering
• 5+ years of hands-on experience in Chip Top Physical Design/Backend at leading semiconductor companies
• Experience working on advanced process technologies (5nm, 3nm, and below)
• Proven experience executing complex block or chip-level projects
• Deep hands-on expertise in RTL2GDS flows, including P&R, STA, Physical Verification (DRC/LVS), Formal Verification, low-power implementation (UPF/CPF), and EMIR
• Mastery of industry-standard EDA tools (Synopsys Fusion Compiler/ICC2 or Cadence Innovus)
• Practical experience handling both complex macro/subsystem-level designs and Full-Chip integration

Nice to have

• Deep understanding of Power & Noise analysis (EM/IR)
• Experience with DFT (Design for Test) integration into the physical design flow
• Background in high-speed interfaces or data center protocols

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.