Principal Design Engineer

The role

The Principal Design Engineer will develop micro-architecture and implementation of front-end circuit design. This includes RTL, synthesis, IP integration, and block-level verification for high performance network controllers.

What you will do

• Develop micro-architecture and implementation of front-end circuit design
• Perform RTL, synthesis, IP integration, and block-level verification
• Drive multiple complex designs from architecture to GDS to production
• Prioritize a dynamic list of multiple tasks
• Plan and prepare for customer meetings

Required qualifications

• Bachelor's degree in EE
• 8+ years experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage
• Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
• Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
• Full chip or block level ownership from architecture to GDS
• Experience with Synopsys and/or Cadence digital design tools/flows
• Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
• Familiarity with UVM based design verification
• Silicon bring-up and debug expertise
• Small-geometry CMOS (≤28nm) design
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks
• Authorized to work in the US and start immediately

Nice to have

• Master's degree
• Firmware development with C-language
• Scripting with Python or other equivalent programming languages
• Development/support for PCIe or Ethernet Switch products

About the company

Astera Labs provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.