Principal Design Verification Engineer (AI Fabric Switches)

The role

You will contribute to the functional verification of designs. You will be responsible for the full life cycle of verification, from planning to writing tests to debugging, collecting and closing coverage.

What you will do

• Manage the full life cycle of verification from planning to writing tests to debugging, collecting and closing coverage.
• Work with software and system validation teams to create test plans and execute them in emulation platforms.
• Develop test-plans and related test-sequences to generate stimuli.
• Work collaboratively with RTL designers to debug failures.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Close coverage to identify verification holes for high quality tape-out.

Required qualifications

• Bachelor's in EE
• 8 or more years experience verifying and validating complex SoC for Server, Storage, and Networking applications
• Knowledge of industry-standard simulators, revision control systems, and regression systems
• Professional attitude with the ability to prioritize a dynamic list of multiple tasks, and work with minimal guidance and supervision
• Entrepreneurial, open-minded behavior and can-do attitude
• Experience with full verification lifecycle based on System Verilog/UVM/C/C++
• Proven ability to mix and deploy hybrid techniques as in both directed and constrained random
• Experience with different ways to bug and coverage hunting
• Must be able to work independently to develop test-plans, and related test-sequences to generate stimuli and work collaboratively with RTL designers to debug failures
• Identify and write all types of coverage measures for stimulus and corner-cases
• Close coverage to identify verification holes for high quality tape-out
• Authorized to work in the US and start immediately

Nice to have

• Masters
• Experience with System Verilog, C, C++, Python or other scripting languages
• Experience in formal methods
• Working experience with scripting tools (Perl/Python) to automate verification infrastructure
• Prior experience using Verification IPs from 3rd party vendors with one or more communication protocols such as PCI-Express (Gen-3 and above), Ethernet, InfiniBand, DDR4/5, NVMe, USB, etc.
• Experience with directed test based methodologies, cache verification and formal methods

About the company

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. The company's Intelligent Connectivity Platform integrates semiconductor-based technologies with the COSMOS software suite.