Celerocommunicationsinc
Principal PLL Design Engineer
Irvine, CA or San Jose, CA. Posted 7 months ago
The role
This person will architect and design advanced clocking circuits for optical transceivers, high-speed SerDes, and high-performance ADC/DAC systems. The role involves designing analog/mixed-signal PLL building blocks and conducting lab bring up and system-level simulations.
What you will do
- Understand trade-offs between different PLL topologies to meet specifications
- Architect, design and simulate analog/mixed-signal PLL building blocks at transistor level
- Address challenges in advanced node technologies
- Supervise and verify layouts produced by layout engineers
- Be responsible for PLL bring up in the lab
- Conduct performance characterization using lab equipment
- Conduct comprehensive system-level simulations and validation
Required qualifications
- Master’s degree and/or PhD in Electrical Engineering or related fields
- 5+ years of relevant experience in PLL design
- Production level tape-out experience
- Extensive experience with advanced node technologies (16nm/12nm, 7nm, 5nm, 3nm, 2nm processes)
- Deep understanding of phase noise analysis, VCO design, LDOs and supporting circuitry associated with PLLs
- Proficient in cadence virtuoso, electromagnetic simulator (e.g., EMX/HFSS), and MATLAB for system-level modelling
- Strong communication and documentation skills
About the company
A fast-growing semiconductor startup developing High-Speed Interconnect solutions for optical networks.