Principal Physical Design Engineer

The role

This person will lead the transformation of complex circuit designs into manufacturable silicon. You will drive physical implementation flows and collaborate with architecture, RTL, circuit design, and verification teams.

What you will do

• Own physical implementation of System-on-Chips or complex digital blocks
• Manage floor-planning, bump planning, power grid design, and clock tree synthesis
• Resolve timing, congestions, and EM/IR issues with Frontend Designers
• Run Static Timing Analysis and physical verification
• Fix Design Rule Checking and Layout Versus Schematic violations
• Drive automation and improve flow robustness using Tcl, Python, or Perl
• Partner with architects, logic designers, and analog design team for tapeout readiness

Required qualifications

• 7+ years of relevant ASIC physical design experience (depending on degree level)
• Deep tapeout experience in advanced technology nodes (e.g., 7nm, 5nm, 3nm)
• Advanced proficiency with industry-standard EDA tools from vendors like Cadence (e.g., Innovus, Tempus, Voltus, Pegasus, Calibre)
• Expertise in physically aware synthesis, power domain analysis, and Electromigration/IR-drop (EM/IR) cleanup

About the company

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure.