Principal Physical Verification Engineer

The role

This person will lead full chip Physical Verification efforts and own execution plans and schedules. They will work with Analog and Physical Design teams to ensure design quality and tapeout readiness on advanced TSMC nodes.

What you will do

• Lead full chip Physical Verification effort
• Own execution plans and schedules for full-chip
• Drive accountability for quality, milestones, and tapeout readiness
• Conduct full chip and blocks PV checks
• Work with internal analog team to ensure clean IP delivery
• Run and analyze DRC/ERC/LUP/PERC results
• Partner with analog, block, and chip top owners to ensure clean floorplan
• Provide early guidance on corner case requirements
• Influence floorplan constraints, hierarchy, and implementation strategy
• Participate in tapeout readiness reviews

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering or related field
• 7+ years of experience with full-chip verifications
• Hands-on experience with Physical Verification tools (Synopsys IC Validator (ICV), Siemens Calibre)
• Able to assemble a flow to support block/chip level PV
• Strong expertise in floorplanning to avoid DRC/LVS issues
• Provide guidance to analog IP team to allow for clean integration

Nice to have

• Experience in advanced technology nodes (7nm, 5nm, 3nm)
• Automation skills using Tcl, Python, or shell scripting

About the company

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure.