High-Speed Analog Layout Design Engineer

The role

This person will lead the physical layout design of complex analog and mixed-signal IP blocks. They will work on ADCs, DACs, PLLs, and other high-performance circuits for optical communication systems.

What you will do

• Lead and own the physical layout design of complex analog/mixed-signal macros from floor planning through final verification
• Collaborate with schematic designers to create layout solutions for performance, matching, symmetry, and reliability
• Mentor and guide junior layout engineers and contractors across multiple time zones
• Perform and debug full hierarchy LVS, DRC, PERC, ERC, and other signoff checks
• Contribute to chip-level planning including top-level floor planning, block integration, power grid implementation, and signal routing
• Participate in layout design reviews and provide technical leadership
• Support automation initiatives through scripting and tool customization

Required qualifications

• Minimum 1+ years of hands-on analog/mixed-signal layout design experience and in advanced CMOS/FinFET technologies
• Proven track record of top-level integration IP layout macros and preparing IPs for handoff to Physical Design
• Proven leadership in owning major IP layout macros or full-chip-level layout at FinFET nodes
• At least 1+ years of experience with TSMC FinFET process nodes (N3, N5, N7, or N16)
• Deep understanding of device physics, layout-dependent effects (LOD, WPE, OSE, LDE, etc.), and their impact on circuit performance
• Strong expertise in layout best practices for device matching, noise isolation, ESD protection, symmetry, and parasitic minimization
• Proficiency in floor planning, hierarchical block integration, routing strategy, and power/ground grid design
• Expertise with Cadence Virtuoso, Calibre, Pegasus, and other layout and verification tools
• Familiarity with layout verification flows, including LVS, DRC, PERC, Density, DFM, ERC, and Antenna rules
• Experience working in collaborative environments with international and remote teams
• Strong documentation and communication skills
• Experience using revision control systems for layout design management

Nice to have

• TSMC preferred
• Exposure to optical or high-speed analog interfaces is a strong plus
• Working knowledge of SKILL, TCL, or Python for layout automation or design flow optimization
• Proven ability to collaborate with international teams (U.S., Canada, Argentina)
• Strong organizational skills with high attention to detail and follow-through
• Ability to multi-task and prioritize in a fast-paced, dynamic environment
• Proactive, eager-to-learn mindset with excellent problem-solving skills

Benefits

• The chance to play a foundational role at a high-growth semiconductor start-up
• Exposure to a wide variety of cross functional teams
• A collaborative, international team culture where ideas and initiative are valued
• The opportunity to grow alongside Celero as we scale and shape the future of our industry

About the company

Celero Communications is a fast-growing semiconductor startup developing high-performance coherent DSP technology for next-generation AI infrastructure.