Sr Staff Physical Design - SOC Top Lead

The role

The Lead Physical Design Engineer will take end-to-end ownership of SOC-top for next-generation SoCs. This role involves driving the full chip from block integration through timing, power, signal integrity, and physical closure to tapeout-ready GDS.

What you will do

• Full-chip integration including floorplanning, power planning, macro/hard-IP placement, and block partitioning
• Full-chip STA across all corners/modes and chip-level constraint ownership
• Full-chip power planning, PDN design/analysis, rail architecture, and power-gating strategy coordination
• DRC/LVS/antenna closure at the top level, seal ring integration, and coordination of ECO cycles
• Crosstalk, di/dt, and chip-level noise closure
• Top-level clock tree strategy and CTS coordination
• Chip-level scan stitching, MBIST/JTAG integration, and coordination with DFT lead
• Bump/ball map coordination, IO ring planning, and package-aware floorplanning
• Sign-off checklist ownership and final GDS handoff
• Technical leadership and mentoring block-level PD engineers

Required qualifications

• Master's degree in Electrical Engineering with 5+ years of industry experience or PhD in Electrical Engineering with 3+ years of industry experience
• 8-12+ years of physical design experience
• At least 2-3 full tapeouts at the chip-top/SoC integration level
• Deep hands-on experience with advanced nodes
• Proven track record owning full-chip timing closure across multiple corners/modes on a complex SoC
• Strong PDN/IR-drop/EM analysis experience (Voltus or equivalent)
• Experience with chip-level DFT integration (scan stitching, MBIST, JTAG)
• Tool fluency: Innovus (or ICC2), Tempus/PrimeTime, RedHawk, Calibre
• Demonstrated ability to lead technically without direct reports
• Excellent scripting skills in TCL, shell and python

Nice to have

• Familiarity with package co-design (flip-chip/BGA, C4 bumps, ball map)
• Experience with non-standard/novel architectures (dataflow, tiled, NoC-based)
• Knowledge of computer architecture
• Knowledge of physical design and ASIC implementation
• Experience in full chip sign off convergence
• Knowledge of circuit design, device physics, deep sub-micron technology and its implications to physical design
• Proficiency with industry-grade physical design flow
• Experience in integrating analog or mixed-signal macro on top-level design

Benefits

• Competitive base salary
• 10% annual bonus
• Meaningful equity
• 401(k) match
• Company-paid benefits
• Paid parental leave
• Flexibility

About the company

Efficient Computer is rethinking computing from the ground up to solve energy challenges in AI. Their Fabric architecture delivers significant energy efficiency improvements for general-purpose computation.