Principal Physical Design Engineer (RTL-to-GDSII)

The role

The Principal Physical Design Engineer will lead the implementation of high-speed blocks and SoCs from Synthesis through Sign-off. This role involves optimizing PPA, building scalable methodologies, and collaborating with RTL, Architecture, and DFT teams.

What you will do

• Lead the implementation of massive, high-speed blocks/SoCs from Synthesis through Sign-off using the Cadence Digital Suite.
• Analyze and optimize the interplay between library cells, metal stacks, and tool engines to optimize PPA.
• Build and refine a Push-Button style execution methodology.
• Collaborate with RTL, Architecture, and DFT teams to influence design decisions early.
• Identify execution pipeline bottlenecks and architect automated solutions.
• Build technical bridges with Front-End, Foundry, and EDA vendors.
• Mentor the PD team to elevate technical competence.

Required qualifications

• 14+ years in Physical Design with a proven track record of multiple sub-5nm tape-outs.
• Mastery of Cadence Innovus, Tempus, Joules, Pegasus, and Voltus.
• Deep understanding of sub-5nm physics: EUV constraints, multi-patterning, FinFET and IR/EM challenges.
• Expert-level knowledge in Static Timing Analysis (STA), Physical Verification (PV), and Power Integrity (PI) and ECO methodology.
• Proficiency in Tcl and Python to develop custom flow wrappers and data-mining tools for PPA analysis.

About the company

EnCharge AI is a leader in advanced AI hardware and software systems for edge-to-cloud computing. Launched in 2022, it is led by veteran technologists with backgrounds in semiconductor design and AI systems.