Enchargeai36

Senior Staff / Principal SOC Floorplan Lead

Bangalore. Posted 3 months ago

The role

The SoC Floorplan Lead will own the physical foundation of next-generation AI and Data Center SoCs. This person will bridge architecture, logic design, and physical design to achieve best-in-class Power, Performance, and Area.

What you will do

  • Own the SoC-level floorplan from concept to tape-out for high-performance chips on advanced process nodes.
  • Partner with Architecture and RTL teams to provide early physical feasibility feedback.
  • Drive block partitioning, shape optimization, and data-flow planning.
  • Lead bump planning and IO ring definition.
  • Work with packaging teams on flip-chip/advanced packaging constraints.
  • Manage placement and custom routing strategies for critical Analog/Mixed-Signal IPs, high-speed SerDes, PLLs, and clock distributions.
  • Design and analyze the top-level power grid.
  • Manage macro placement, block-level pin assignments, and top-level feedthrough planning.
  • Build and maintain scalable Floorplanning workflows and scripts.

Required qualifications

  • 12 + years of hands-on experience in Physical Design SoC Floor planning
  • At least 3 years acting as a lead or primary owner of SoC-level Floorplanning
  • Proven track record of taping out large, complex chips for Data Center, Networking, or AI/Machine Learning applications
  • Deep understanding of how RTL structures and architectural decisions impact physical design PPA
  • Extensive experience with bump planning, flip-chip package requirements, and die-to-package co-optimization
  • Strong knowledge of analog/mixed-signal IP integration, shielding, and custom routing constraints
  • Expertise with industry-standard physical design tools (Cadence Innovus)
  • BS, MS, or Ph.D. in Electrical Engineering, Computer Engineering, or a related field

Nice to have

  • Experience with multi-die / chiplet integration (2.5D, 3D packaging, interposers, UCIe)
  • Strong scripting and automation skills (Tcl, Python, Perl, Makefile)
  • Knowledge of advanced clocking architectures (H-trees, meshes) for highly synchronous AI fabrics

Benefits

  • Opportunity to build ground-up architecture and see ideas taped out in cutting-edge silicon
  • Competitive start-up equity packages
  • Flat, collaborative, and bureaucracy-free environment

About the company

enchargeai36 is a high-energy start-up with a flat, collaborative, and bureaucracy-free environment surrounded by top-tier industry veterans.

Senior Staff / Principal SOC Floorplan Lead at Enchargeai36 | JobZoey