Senior PD Engineer: Synthesis & STA

The role

This person will take end-to-end ownership of logic synthesis and quality signoff for key blocks and sub-chips. They will act as a bridge between front-end design and back-end physical implementation teams.

What you will do

• Drive and own the complete logic synthesis process for all designated blocks and sub-chips.
• Define, execute, and monitor rigorous sanity checks to achieve a high-quality Synthesis Signoff.
• Work closely with RTL design engineers to ensure the delivery of a clean, fully linted netlist.
• Deep dive into timing paths to ensure Levels of Logic (LOL) are strictly controlled.
• Provide actionable RTL coding guidelines, structural recommendations, and micro-architecture inputs.
• Progressively take on responsibilities in PNR execution, STA, and full-chip timing convergence.

Required qualifications

• 5 to 8 years of proven experience in ASIC/SoC Logic Synthesis and Static Timing Analysis.
• Hands-on experience with industry-standard synthesis tools.
• Proficiency with STA signoff tools (e.g., Tempus, PrimeTime).
• Strong foundational knowledge of STA, timing constraints (SDC), delay calculation, and multi-mode multi-corner (MMMC) analysis.
• Deep understanding of Verilog/SystemVerilog, digital logic design, and RTL linting/CDC tools.
• Proven ability to analyze datapath architectures, identify logic bottlenecks, and recommend specific RTL changes to reduce logic depth.
• Proficiency in Tcl, Python, or Perl for developing and maintaining synthesis flow automation and customized reporting scripts.
• Excellent analytical and communication skills to negotiate solutions between RTL and Physical Design teams.

Nice to have

• Strong preference for Cadence Genus.
• Prior exposure to Place and Route (PNR) flows (e.g., Innovus, ICC2).
• Experience with Formal Verification / Logic Equivalence Checking (LEC/Formality).
• Knowledge of advanced technology nodes (e.g., 5nm, 3nm).

About the company

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