Senior ASIC (Front-End) Design Engineer

The role

You will be responsible for all aspects of digital SoC design from micro-architecture specification to static timing analysis. You will work with system architects, software, hardware, and verification engineers to deliver advanced automotive communication semiconductors and systems.

What you will do

• Manage all aspects of digital SoC design including micro-architecture specification, RTL, verification, synthesis, lint, CDC, LEC, and static timing analysis.
• Deliver designs meeting target power, performance, and area goals.
• Plan, architect, design, implement, and deliver advanced automotive communication semiconductors and systems.
• Flesh out product definitions with precise specifications of ASIC internal and external interactions, data flow, processing algorithms, resource management, and software interfaces.

Required qualifications

• BS and/or MS in Electrical Engineering, Computer Science, or related field
• Minimum 10+ years of ASIC RTL design and/or architecture experience
• Proven track record with the development of complex SoCs
• Strong understanding of digital design fundamentals and methodologies
• In-depth knowledge of Verilog/System Verilog and simulation tools
• Self-motivated and able to work effectively both independently and in a team

Nice to have

• Networking (Ethernet MAC, PHY, Switching, TCP/IP, security, PCIe and other industry standard protocols)
• Video standards, protocols, processing
• Digital signal processing filters
• IP integration (SerDes, controllers, processors, etc.)
• Perl, TCL, C/C++, Make
• Excellent communication/documentation skills
• Attention to details
• Collaboration across multidisciplinary and international teams

Benefits

• Pre IPO stock options
• Competitive base salary
• Flexible hours
• Medical, dental and vision insurance

About the company

Ethernovia is developing Ethernet-based networks for software-defined and autonomous vehicles, robotics and other intelligent machines. The company has secured $154M in total funding to date.