Janestreet
ASIC Physical Design Engineer
London, England, United Kingdom. Posted 7 months ago
The role
An ASIC Physical Design Engineer will design, test and deploy advanced hardware. You will work as part of the Ultra Low Latency team and collaborate with trading, networking and research infrastructure areas.
What you will do
- Own a PD flow end-to-end
- Read and write RTL
- Reason about design decisions that cross the front-end/back-end boundary
- Work across the chip design process
Required qualifications
- 8+ years hands-on experience building and running modern physical design flows (e.g., floorplanning, place and route, timing closure, physical verification, power analysis)
- Ability to read and write RTL
- Understand how front-end design decisions affect physical implementation and vice versa
- Experience programming in a high-level language (Python, C++, Haskell, etc.)
- Fluent in English
Nice to have
- Verilog or SystemVerilog
About the company
Jane Street is a firm with areas including trading, networking and research infrastructure.