Senior ASIC Design Verification Engineer

The role

The Senior ASIC Design Verification Engineer will verify the functionality, performance, and robustness of custom silicon designs. This role involves defining verification approaches and working with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.

What you will do

• Develop and execute verification plans for block-level, subsystem-level, and full-chip environments.
• Build SystemVerilog/UVM test benches, including agents, monitors, scoreboards, checkers, and coverage models.
• Write SystemVerilog Assertions (SVA) and integrate formal verification.
• Drive constrained-random and directed testing strategies.
• Run simulations, triage failures, and drive root-cause analysis.
• Implement and maintain functional coverage, code coverage, and assertion coverage.
• Manage regression testing, simulation farms, and CI pipelines.
• Participate in design reviews and microarchitecture discussions.
• Work with architecture, RTL design, DFT, firmware, physical design, and silicon validation engineers.
• Support silicon bring-up and post-silicon validation.

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of experience in ASIC/SoC verification.
• Solid understanding of SystemVerilog, digital logic, RTL design, and hardware verification flows.
• Proficiency with a simulation (VCS, Xcelium, Questa), waveform debug (Verdi, SimVision), coverage tool, and scripting languages (ex: Python, Perl, TCL).
• Experience with testplanning, UVM-based testbench development, constrained-random testing, functional coverage, and SystemVerilog assertions.
• Experience with regression management, coverage analysis, revision control (Git), and CI/CD automation.
• Understanding of several industry-standard interfaces (ex: APB/AHB/AXI).
• Familiarity with embedded processor-based designs and firmware/bare metal coding (ex: C, C++).

Nice to have

• Experience with developing and integrating reference models.
• Understanding of low power verification.
• Familiarity with gate-level simulation and analog behavioral models.
• Involvement in post-silicon validation planning and execution.
• Experience working in cross-functional, geographically distributed teams.
• Experience in space, telecom, or RF/digital mixed systems

Benefits

• Paid time off
• Medical/dental/vision coverage
• Life insurance
• Paid parental leave
• Many other perks

Before you apply

• Must be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.
• The role has access to information and items controlled by U.S. export control regulations (ITAR).

About the company

K2 is building the largest and highest-power satellites ever flown to deliver unmatched capability at constellation scale. The company is a high-growth Series D-funded company mass-producing satellite platforms for missions from LEO to deep space.