Principal ASIC Physical Design Engineer

The role

You will lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the full physical design flow from RTL handoff to GDSII and manage external physical design partners.

What you will do

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place & route, clock tree synthesis (CTS), static timing analysis (STA), physical verification (DRC/LVS), and sign-off.
• Develop and maintain physical design methodologies, scripts, and automation to optimize PPA.
• Collaborate with front-end and verification teams to ensure clean handoffs, timing closure, and efficient design iteration.
• Drive timing closure across multiple voltage and process corners.
• Partner with package, SI/PI, and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and service vendors.
• Work with EDA vendors to debug and optimize tool flows, and evaluate new methodologies.
• Support chip bring-up and debug through close collaboration with post-silicon and test teams.
• Support your product through production and spaceflight.
• Act as technical leader and subject matter expert to teach, grow, and mentor others.

Required qualifications

• Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC physical design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using industry tools (Synopsys, Cadence, or Siemens).
• Strong hands-on experience with timing closure, IR drop analysis, and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience managing or coordinating offshore/outsourced PD teams or vendors.
• Familiarity with DFT integration, STA sign-off, and power domain implementation (UPF/CPF).
• Excellent communication, leadership, and cross-functional collaboration skills.

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Paid time off
• Medical/dental/vision coverage
• Life insurance
• Paid parental leave
• Many other perks

Before you apply

• Must be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

About the company

K2 is building the largest and highest-power satellites ever flown for missions from LEO to deep space. The company is mass-producing high-power satellite platforms and is a high-growth Series D-funded company.