Principal ASIC Synthesis and Timing Engineer

The role

You will lead the implementation of complex SoCs for next-generation satellite and space systems. You will own constraints, RTL-to-synthesis flow, and timing closure, and manage external physical design partners.

What you will do

• Own the complete RTL-to-synthesis flow, including block and top-level synthesis.
• Develop and maintain design methodologies, scripts, and automation to optimize performance, power, and area.
• Drive timing closure across multiple voltage and process corners, with sign-off using foundry-qualified tools.
• Own Lint, CDC and UPF checks and close out issues.
• Develop an end-to-end formal verification methodology between RTL and post-layout netlist.
• Manage and technically guide external physical design partners and service vendors.
• Work with EDA vendors to debug and optimize tool flows.
• Support chip bring-up and debug with post-silicon and test teams.
• Support the product through production and spaceflight.
• Act as technical leader and mentor to the team.

Required qualifications

• B.S. or M.S. in Electrical Engineering, Computer Engineering, or related field.
• 10+ years of experience in ASIC design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence, or Siemens tools.
• Hands-on experience with timing closure, IR drop analysis, low power implementation and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage, and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience in design convergence with offshore or outsourced physical design teams or vendors.
• Able to resolve formal verification issues.
• Able to analyze and fix VCLP issues regarding UPF.
• Experience with logic equivalence check debug, functional ECO development and implementation, and low power checker validation of UPF.
• Familiarity with DFT integration and STA sign-off with functional ECO implementation.
• Excellent communication, leadership, and cross-functional collaboration skills.

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs.
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Comprehensive benefits package.
• Paid time off.
• Medical, dental and vision coverage.
• Life insurance.
• Paid parental leave.
• Many other perks.

Before you apply

• Must be a U.S. person as defined by 22 C.F.R. § 120.15, or otherwise eligible for a federally issued export control license, due to ITAR access requirements.
• U.S. persons include U.S. citizens, lawful permanent residents, and certain protected individuals such as refugees, asylees and American Samoans.

About the company

K2 Space is building the largest and highest-power satellites ever flown, with over $1 billion in funding and over $1 billion in signed contracts. The company plans multiple launches in 2027 and aims to scale to 100 satellites a year.