Principal ASIC Physical Design Engineer

The role

You will lead the implementation of complex SoCs for next-generation satellite and space systems. You will own the physical design flow from RTL handoff to GDSII and manage external physical design partners.

What you will do

• Own the complete RTL-to-GDSII flow: synthesis, floorplanning, place and route, clock tree synthesis, static timing analysis, physical verification and sign-off.
• Develop and maintain physical design methodologies, scripts and automation to optimize performance, power and area.
• Collaborate with front-end and verification teams for clean handoffs and timing closure.
• Drive timing closure across multiple voltage and process corners.
• Partner with package, SI/PI and test teams for package-aware floorplanning and chip-to-board integration.
• Manage and technically guide external physical design partners and service vendors.
• Work with EDA vendors to debug and optimize tool flows.
• Support chip bring-up and debug with post-silicon and test teams.
• Support the product through production and spaceflight.

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, or a related field.
• 10+ years of experience in ASIC physical design for high-performance SoCs.
• Proven end-to-end expertise in RTL-to-GDSII flows using Synopsys, Cadence or Siemens tools.
• Strong hands-on experience with timing closure, IR drop analysis and ECO implementation.
• Deep understanding of physical design constraints for multi-clock, multi-voltage and hierarchical SoCs.
• Experience with advanced FinFET process nodes.
• Prior experience managing or coordinating offshore or outsourced physical design teams or vendors.
• Familiarity with DFT integration, STA sign-off and power domain implementation (UPF/CPF).
• Excellent communication, leadership and cross-functional collaboration skills.
• Act as technical leader and subject-matter expert, teaching, growing and mentoring others.

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience driving tapeouts through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Paid time off
• Medical, dental and vision coverage
• Life insurance
• Paid parental leave
• Many other perks
• Equity in the company

Before you apply

• The person hired must be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license, due to ITAR requirements.

About the company

K2 Space is building the largest and highest-power satellites ever flown. The company is Series D-funded and has over $1 billion in signed contracts with commercial and US government customers.