Senior ASIC Physical Design Engineer

The role

This person will implement advanced SoCs for next-generation satellite and space systems. The work covers the full physical design flow, from synthesis to GDSII, with timing closure, PPA optimization and support for design integration with external partners.

What you will do

• Execute the complete physical design flow for complex SoC blocks and top-level integration, including synthesis, floorplanning, place & route, CTS, STA and physical verification.
• Perform timing closure and optimization across multiple corners and modes using industry-standard tools.
• Collaborate with front-end, verification and DFT teams for clean handoff and predictable convergence.
• Work with external physical design service providers and internal leads to review deliverables, resolve issues and keep schedules aligned.
• Develop and maintain scripts and automation to improve flow efficiency and consistency.
• Support physical sign-off activities, including DRC/LVS, IR drop, EM and power analysis.
• Assist in chip-level integration, ECOs and tapeout preparation.
• Contribute to methodology development, tool evaluation and flow documentation.
• Support your product through production and spaceflight.

Required qualifications

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering or a related field.
• 5 to 10 years of experience in ASIC physical design for complex SoCs.
• Hands-on experience with industry-standard tools (Synopsys ICC2/Fusion Compiler, Cadence Innovus, or equivalent).
• Strong understanding of timing analysis, power optimization and physical verification flows.
• Experience with hierarchical or flat SoC design methodologies.
• Familiarity with FinFET technologies.
• Working knowledge of DFT, UPF/CPF power intent and ECO implementation.
• Strong problem-solving skills and ability to work cross-functionally in fast-paced environments.
• Must be a U.S. Person as defined by 22 C.F.R. § 120.15, or otherwise eligible for a federally issued export control license.

Nice to have

• Exposure to radiation-hardened or space-qualified ASICs.
• Experience with chip-package co-design or advanced packaging (2.5D/3D).
• Familiarity with physical design service vendor management or offshore collaboration.
• Experience with sign-off through TSMC.
• Experience with Gate-All-Around technologies.
• Experience working in cross-functional, geographically distributed teams.

Benefits

• Paid time off.
• Medical, dental and vision coverage.
• Life insurance.
• Paid parental leave.
• Many other perks.
• Equity in the company.

Before you apply

• Must be a U.S. Person as defined by ITAR (U.S. citizen, lawful permanent resident, or certain protected individual), or otherwise eligible for a federally issued export control license.
• You do not need to meet 100% of the preferred skills and experience to apply.

About the company

K2 Space is building the largest and highest-power satellites ever flown, and is a high-growth company that has raised Series D funding. It is an Equal Opportunity Employer.