Senior Serdes Characterization & Post-Silicon Validation Engineer

The role

This person will bring up, characterize, and validate high-speed SerDes interfaces in complex SoCs. They will work with multiple engineering teams to take interfaces from first silicon through product integration and system-level operation.

What you will do

• Lead post-silicon bring-up and characterization of high-speed NRZ and PAM4 SerDes.
• Develop and execute electrical characterization plans.
• Characterize TX eye quality, jitter, amplitude, linearity, equalization, RX sensitivity, BER, and CDR performance.
• Validate TX/RX equalization including FFE, CTLE, DFE, adaptation, and link-training behavior.
• Perform BER and stress testing across representative and worst-case channels.
• Debug complex link issues spanning SerDes IP, clocks, power, package, PCB/channel, firmware, and digital logic.
• Correlate silicon measurements with SerDes models, simulations, and channel/SI analysis.
• Partner with firmware and digital teams on SerDes configuration and system-level link bring-up.
• Develop automated characterization and regression environments.
• Support the transition from chip-level characterization to product integration and system-level validation.

Required qualifications

• BS/MS in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of high-speed SerDes characterization, post-silicon validation, signal integrity, or related experience.
• Strong understanding of high-speed serial-link fundamentals, including NRZ/PAM4 signaling, equalization, CDR, jitter, BER, channel loss, and link budgets.
• Deep hands-on experience with high-bandwidth oscilloscopes, BERTs, pattern generators, VNAs, TDR/TDT, and high-speed electrical measurement equipment.
• Experience with eye diagrams, jitter decomposition, bathtub curves, BER testing, stressed-eye testing, and receiver sensitivity characterization.
• Strong understanding of package/PCB channels, insertion/return loss, crosstalk, reflections, and channel de-embedding.
• Experience developing automated characterization environments using Python or similar scripting languages and instrument-control interfaces.
• Strong debugging skills across silicon, package, PCB, firmware, and system boundaries.
• Ability to work closely with SerDes IP/design, SI, package, board, firmware, and digital teams.

Nice to have

• Experience with 112G+ PAM4 SerDes characterization and validation.
• Experience with Ethernet, PCIe, JESD204, Interlaken, or chip-to-chip interfaces.
• Experience with compliance testing and high-speed interface standards.
• Familiarity with SerDes behavioral/channel models and simulation-to-measurement correlation.
• Experience with SerDes IP integration and validation from third-party IP vendors.
• Experience with advanced package and high-loss PCB channels.
• Familiarity with high-speed clocking, PLLs, reference-clock jitter, and power-supply noise effects on SerDes performance.
• Experience with automated PVT characterization and large-scale measurement data analysis.

Benefits

• Paid time off
• Medical/dental/vision coverage
• Life insurance
• Paid parental leave
• Many other perks

Before you apply

• Must be a U.S. person as defined by 22 C.F.R. § 120.15 or otherwise eligible for a federally issued export control license.

About the company

K2 is building the largest and highest-power satellites ever flown. They are mass-producing high-power satellite platforms for missions from LEO to deep space.