Senior Hardware Design Engineer

The role

Senior Hardware Design Engineers design component units of the Reconfigurable Dataflow Unit (RDU) ASICs. You will author microarchitecture specifications, write and debug SystemVerilog RTL, and carry blocks through implementation, tapeout, and silicon bring-up.

What you will do

• Author sections of the microarchitecture specification for compute, memory, or networking subsystems.
• Code, integrate, and debug SystemVerilog RTL for assigned blocks.
• Meet Power, Performance, and Area (PPA) targets using advanced digital design techniques.
• Partner with design verification and physical design engineers to converge on functionality, timing, and area.
• Implement SystemVerilog Assertions (SVA) and run lint, CDC, and LEC flows.
• Participate in design reviews and incorporate feedback.
• Support post-silicon bring-up and debug for owned blocks.
• Contribute to design flow improvements including AI and automation in EDA tool methodologies.

Required qualifications

• Master's degree in Computer Engineering or Electrical Engineering with 3–5 years of relevant experience, or Bachelor's degree with 5–7 years.
• Solid foundation in computer architecture and digital logic design.
• Strong SystemVerilog RTL design skills for high-speed, high-performance ASICs.
• Experience making design decisions that trade off Power, Performance, and Area (PPA).
• Working knowledge of industry-standard interconnects and protocols (e.g., AXI, PCIe, Ethernet, HBM/DDR).
• Experience with digital logic synthesis tools and Static Timing Analysis (STA).
• Proficiency with industry-standard tools for linting, Clock Domain Crossing (CDC), and Logical Equivalence Checking (LEC).
• Experience implementing SystemVerilog Assertions (SVA) to check design intent.
• Familiarity with tools and simulators for hardware performance analysis and tuning.
• Familiarity with Git for managing release cycles.
• Scripting skills in Python and Linux shell.
• Ability to work onsite in San Jose, CA or Austin, TX.

Nice to have

• Exposure to a full ASIC development cycle through tapeout and production silicon.
• Interest in or knowledge of AI workload acceleration techniques.
• Experience with low-power design techniques (clock gating, DVFS) at advanced process nodes.
• Exposure to emulation or FPGA prototyping platforms for pre-silicon validation.

Benefits

• Base salary plus equity
• 95% premium coverage for employee medical insurance
• 77% premium coverage for dependents
• Health Savings Account (HSA) with employer contribution
• Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans
• Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care
• Headspace subscription
• Gympass+ membership
• One Medical membership
• Counseling services with an Employee Assistance Program

Before you apply

• You must submit an application form for each position for which you believe you are qualified.

About the company

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. Its core technology is the RDU (Reconfigurable Dataflow Unit).