Director of ASIC Design Verification

The role

The Director of ASIC Design Verification will own end to end verification for next generation RDU chips. You will lead a team of 8-10 engineers and act as the technical authority on verification methodology and strategy.

What you will do

• Own pre-silicon functional and performance verification for SambaNova ASICs
• Define verification architecture, strategy, schedules, and DV environments
• Serve as the technical authority on verification and lead debug on hard failures
• Set and defend the DV schedule and own tape-out readiness sign-off
• Support lab functional validation and bring-up debug for first silicon
• Lead, coach, and retain principal-level verification engineers
• Own team growth, staffing, leveling, and interview loop design
• Own the DV methodology end to end including reuse strategy and sign-off criteria
• Lead development of test benches, agents, checkers, and stimulus
• Direct emulation and FPGA prototyping strategy and manage EDA vendor relationships

Required qualifications

• BS in EE, CS, or CE with 12+ years (or equivalent) of industry experience in ASIC design verification
• 5+ years managing design verification engineers, including hiring and performance management
• Experience leading senior and principal-level engineers
• Track record of inheriting an established verification environment and evolving it
• Deep, current technical expertise in verification
• Full-cycle DV from planning through tape-out and into production silicon on at least one complex ASIC or large subsystem
• Deep hands-on foundation in SystemVerilog, SVA, Python, and industry verification methodologies such as UVM, OVM, or VMM
• Experience through silicon bring-up, including lab functional validation and debugging first-silicon issues
• Working knowledge of machine learning SoCs or microprocessors (CPU/GPU) and modern computer architecture
• Excellent communication skills

Nice to have

• MS or PhD in EECS with 15+ years of experience in ASIC design verification
• Multiple large-scale, high-impact chips led to silicon
• Scaling a DV team through a step change in headcount or chip complexity
• Owning or directing post-silicon functional validation in a lab environment
• Deep understanding of performance verification methodology
• High-performance interconnect protocols (PCIe, Ethernet) and memory subsystems
• Advanced TSMC nodes and modern multi-die or chiplet verification challenges
• Emulation and FPGA prototyping platforms
• Managing cross-site or distributed teams
• Fluency with Claude or other AI tools applied to verification and flow development

Benefits

• Base salary plus equity
• 95% premium coverage for employee medical insurance
• 77% premium coverage for dependents
• Health Savings Account (HSA) with employer contribution
• Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans
• Flexible Spending Account (FSA) options including Health Care, Limited Purpose, and Dependent Care
• Headspace subscription
• Gympass+ membership
• One Medical membership
• Counseling services with an Employee Assistance Program

Before you apply

• You must submit an application form for each position for which you believe you are qualified

About the company

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. Its core technology is the RDU (Reconfigurable Dataflow Unit).