Principal RTL Design Engineer

The role

This person will own the microarchitecture and RTL for the next-generation Reconfigurable Dataflow Unit (RDU). They will manage blocks from specification through tape-out, managing power, performance, and area trade-offs.

What you will do

• Own the microarchitecture and RTL for a major block or subsystem of the RDU
• Write, integrate, and debug synthesizable SystemVerilog RTL
• Own PPA for your area by hitting aggressive frequency targets
• Drive timing closure and design quality including synthesis, STA, lint, CDC, and LEC
• Partner with design verification to define verification intent and support debug
• Work with architects and software teams to prototype and evaluate features
• Drive AI, automation, and new EDA tool methodologies into the design flow
• Set the technical bar in design reviews and mentor design engineers

Required qualifications

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of industry experience in ASIC RTL design
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA
• High-frequency design experience including datapath pipelining, retiming, and critical-path restructuring
• Deep foundation in computer architecture and digital logic design
• Ownership of a complex block or subsystem from microarchitecture specification through tape-out on at least one production ASIC
• Experience converging power, performance, and area against real physical constraints
• Hands-on experience with synthesis and static timing analysis, and with lint, CDC, and LEC quality flows
• Demonstrated technical leadership including setting direction in design reviews and mentoring engineers
• Scripting in Python for design and flow automation

Nice to have

• M.S. or Ph.D. in Electrical Engineering, Computer Engineering, or Computer Science
• Depth in one RDU domain: compute and dataflow datapath, on-chip network and interconnect, or memory subsystem
• Industry-standard interconnects and protocols including AXI, PCIe, Ethernet, and HBM or DDR
• AI and ML workload acceleration techniques, and dataflow or reconfigurable architectures
• Formal property checking applied to design intent
• Advanced TSMC nodes and multi-die or chiplet design
• Performance modeling and analysis to support architectural trade-offs
• Fluency with Claude or other AI tools applied to RTL design and flow development

Benefits

• Base salary plus equity
• 95% premium coverage for employee medical insurance
• 77% premium coverage for dependents
• Health Savings Account (HSA) with employer contribution
• Dental, Vision, Short/Long term Disability, Basic Life, Voluntary Life, and AD&D insurance plans
• Flexible Spending Account (FSA) options like Health Care, Limited Purpose, and Dependent Care
• Headspace subscription
• Gympass+ membership
• One Medical membership
• Counseling services with an Employee Assistance Program

Before you apply

• You must submit an application form for each position for which you believe you are qualified

About the company

SambaNova is a leader in next-generation AI infrastructure, delivering a full-stack inference platform for customers worldwide. Its technology is centered on the RDU (Reconfigurable Dataflow Unit).