Senior HSIO Digital Design Engineer

The role

This role focuses on next-generation HSIO design for Samsung's AI production platforms. The engineer will work on high-speed I/O PHY IP development and collaborate with system and analog teams.

What you will do

• High-Speed I/O PHY IP development
• Collaborate with system and analog teams

Required qualifications

• BS in Electrical Engineering with 5+ Years of experience
• MS in Electrical Engineering with 3+ years of experience
• PhD in Electrical Engineering
• Hands-on experience in High-Speed I/O PHY IP development
• Strong understanding of high-speed serial interconnect protocols and associated design trade-offs
• Solid understanding of how analog and mixed-signal design and verification impact digital-on-top development flows
• Knowledge of Signal Integrity (SI) and Power Integrity (PI) modeling for High-Speed I/O designs
• Understanding of SoC protocols including AXI/CHI/CXS.B/CXL/PCIE/UA-Link

Nice to have

• Familiarity with HSIO PHY layers protocols and architectures

Benefits

• Incentive opportunities
• Medical/Dental/Vision
• 401k
• Charitable giving match
• 4+ weeks of paid time off a year, plus holidays and sick leave
• Stipend for fertility care or adoption
• Caregiver support
• Medical travel support
• On-demand apps and free confidential therapy sessions
• Onsite Café and gym
• Virtual classes
• Flexible environment

Before you apply

• Each candidate is limited to 10 applications across all open jobs within a 6-month period
• AI tools should not be used to generate or assist with submitted content or live interview responses
• By submitting an application, you agree not to disclose any confidential or proprietary information belonging to a current or former employer

About the company

Samsung's San Jose Location Group develops industry leading location technology IP for mobile and wearable applications. The group is part of the broader SoC organization responsible for Exynos line of SoC products.