Samsungsemiconductor

Senior RTL Engineer, IO Die and Interconnect IP

San Jose, California, United States. Posted 2 months ago

The role

You will develop RTL for the IO die and integrate high-speed interconnect IP into chiplet-based architectures. This role involves owning microarchitecture for IO subsystems and collaborating with hardware and software teams to meet performance and power requirements.

What you will do

  • Develop RTL (Verilog/SystemVerilog) for the IO die
  • Integrate UCIe, PCIe, and other high-speed interconnect IP
  • Modify and customize PCIe and other interconnect IP
  • Define and implement die-to-die and chiplet interfaces using UCIe
  • Own the microarchitecture and RTL for IO subsystems
  • Collaborate with verification engineers to develop test plans and debug issues
  • Work with architecture, PHY/SerDes, physical design, and software teams
  • Make design decisions across performance, power, latency, bandwidth, and cost
  • Develop and automate IP integration and RTL assembly flows
  • Communicate with stakeholders to ensure timely delivery

Required qualifications

  • Bachelor’s with 5+ years, or Master’s with 3+ years, or PhD's with 0+ years of industry experience
  • Strong background in microarchitecture and RTL design for complex SoC and die integration
  • 5+ years of experience in RTL development (Verilog/SystemVerilog) for high-speed interconnect and IO subsystems
  • Hands-on experience integrating and configuring interconnect IP such as PCIe, CXL, UCIe, and die-to-die interfaces
  • Experience modifying or customizing third-party interconnect IP
  • Familiarity with UCIe and chiplet-based, multi-die architectures and die-to-die interconnect
  • Solid understanding of PCIe/CXL protocol stacks and the PIPE interface
  • Experience with SoC integration methodologies, IP packaging, and on-chip interface protocols such as AXI, ACE, CHI, or APB
  • Proficiency in scripting (Tcl, Python, or Perl)
  • Experience in AI/ML workloads
  • Strong analytical and problem-solving skills
  • Excellent communication and interpersonal skills

Nice to have

  • Familiarity with agentic AI tools and frameworks

Benefits

  • Incentive opportunities
  • Medical/Dental/Vision
  • 401k
  • Charitable giving match
  • 4+ weeks of paid time off a year, plus holidays and sick leave
  • Stipend for fertility care or adoption
  • Caregiver support
  • Medical travel support
  • On-demand apps and free confidential therapy sessions
  • Onsite Café and gym
  • Virtual classes
  • Flexible environment

Before you apply

  • Each candidate is limited to 10 applications across all open jobs within a 6-month period
  • AI tools should not be used to generate or assist with submitted content or live interview responses

About the company

Samsung Semiconductor is a global leader whose technology solutions power smartphones, electric vehicles, hyperscale data centers, and IoT devices. The AGI Computing Lab focuses on solving complex system-level challenges for future AI/ML workloads.

Senior RTL Engineer, IO Die and Interconnect IP at Samsungsemiconductor | JobZoey