Senior Engineer, Physical Design AI/ML

The role

This role involves designing and implementing machine learning and generative models to optimize chip layout designs for performance, power, and area efficiency. You will automate design implementation and verification steps using exploratory PDKs and research new device architectures for sub-2nm technology nodes.

What you will do

• Design, build, and implement machine learning and generative models to optimize chip layout designs
• Automate and accelerate Design Implementation steps such as Floor-planning, Placement and Routing, Clock Tree Synthesis
• Automate and accelerate Verification steps such as Design Rule Checks (DRC) and Layout versus Schematic (LVS) Checks
• Collaborate to automate all aspects of exploratory PDK generation, including developing automated QA systems
• Apply machine learning techniques to extract and develop correlations among data in different domains
• Develop internal benchmarking capability based on available data, modeling, or learning from multiple sources
• Research and evaluate new device architectures, materials, and integration schemes
• Complete other responsibilities as assigned

Required qualifications

• RTL synthesis, place and route, and timing analysis skills
• Understanding of clock and power delivery network schemes
• Hands-on experience on machine learning or deep learning projects for scientific and/or engineering applications, e.g., regression, surrogate modeling, inverse design, graph neural networks
• Strong Python and/or C++ skills, including expertise in machine learning packages like PyTorch and Tensorflow
• Experience in using Bayesian optimization and/or active learning frameworks for design space exploration
• Expertise with agentic AI frameworks (LangGraph, CrewAI, ADK)

Nice to have

• PhD with industry experience
• Experience in optimization of design-technology co-optimization (DTCO) knobs in advanced logic nodes (2nm or beyond)
• Familiarity with state-of-the-art AI workloads and their compute and memory requirements
• Experience with setting up and optimization of a local, private, compute cluster to run latest LLM models
• Proficiency in EDA tools for synthesis and layout
• Prior experience using generative AI for chip design/optimization

Benefits

• Incentive opportunities based on individual and company performance
• Medical/Dental/Vision
• 401k
• Charitable giving match
• 4+ weeks of paid time off a year, plus holidays and sick leave
• Stipend for fertility care or adoption
• Caregiver support
• Medical travel support
• On-demand apps and free confidential therapy sessions
• Onsite Café and gym
• Virtual classes

Before you apply

• Each candidate is limited to 10 applications across all open jobs within a 6-month period
• AI tools should not be used to generate or assist with submitted content or live interview responses
• By submitting an application, you agree not to disclose any confidential or proprietary information belonging to a current or former employer

About the company

Samsung Semiconductor Inc (SSI) is a global leader whose technology solutions power tools including smartphones, electric vehicles, hyperscale data centers, and IoT devices.