Samsungsemiconductor

Senior Engineer, PLL Design

San Jose, California, United States. Posted a month ago

The role

The candidate will design and develop high-performance PLL and clocking subsystems for RF transceivers, SerDes, and high-speed I/O applications. Work involves designing PLL building blocks, performing system-level modeling, and supporting silicon prototype debug in the lab.

What you will do

  • Design PLLs and clock generation circuits for RF and SerDes applications
  • Design critical PLL building blocks including VCO/DCO, charge pumps, loop filters, phase/frequency detectors, dividers, and phase interpolators
  • Perform PLL system-level modeling, noise analysis, and jitter budgeting using Matlab/Simulink
  • Drive design verification including transistor-level simulation, Monte Carlo analysis, and silicon correlation
  • Collaborate with digital, layout, and systems teams to deliver PLL IPs
  • Support bring-up, characterization, and debug of silicon prototypes in the lab

Required qualifications

  • Master's with 2+ years of experiences or PhD with 0 years of experience in a related field
  • Extensive hands-on experience designing PLLs in deep sub-micron CMOS (5nm-28nm)
  • Experience with at least one of: integer-N, fractional-N, digital PLL, or sub-sampling PLL topologies
  • Deep understanding of PLL system theory: phase noise, jitter, loop dynamics, reference spurs, and fractional spurs
  • Proficiency in IC design CAD tools such as Spectre, SpectreRF, and AMS simulator
  • Strong Matlab/Simulink skills for behavioral modeling and system-level analysis
  • Familiarity with Verilog/SystemVerilog for mixed-signal simulation
  • Solid understanding of layout-sensitive design and ability to guide critical PLL layout
  • Lab characterization experience: phase noise measurement, jitter analysis, and spectrum analysis equipment
  • Experience with RTL design (Verilog/SystemVerilog) to implement PLL-related digital calibration circuits

Benefits

  • Incentive opportunities based on individual and company performance
  • Medical/Dental/Vision
  • 401k
  • Charitable giving match
  • 4+ weeks of paid time off a year, plus holidays and sick leave
  • Stipend for fertility care or adoption
  • Caregiver support
  • Medical travel support
  • On-demand apps and free confidential therapy sessions
  • Onsite Café and gym
  • Virtual classes
  • Flexible environment

Before you apply

  • Each candidate is limited to 10 applications across all open jobs within a 6-month period
  • AI tools should not be used to generate or assist with submitted content or live interview responses
  • By submitting an application, you agree not to disclose any confidential or proprietary information belonging to a current or former employer

About the company

Samsung Semiconductor Inc. (SSI) is a leader in Memory, System, LSI and LCD technologies. US teams contribute to breakthroughs in 5G, SOC, memory and display.

Senior Engineer, PLL Design at Samsungsemiconductor | JobZoey