Staff Engineer, SoC Architecture – Memory Subsystem and Interconnect

The role

This role involves architecting next generation SOCs by leading contributions to Fabric, System cache and DRAM controller sub-system architecture, interface, performance and power tradeoffs. The person will guide the development of architectural features and perform high-level performance modeling and analysis.

What you will do

• Guide development of innovative Fabric, System cache and DRAM controller Architectural and microarchitectural features
• Identify and deliver Fabric, System cache and DRAM controller subsystem architecture proposals
• Evaluate architecture proposal benefits in collaboration with SoC Architects
• Perform high-level performance modeling, simulation and analysis
• Direct and orchestrate performance modeling and studies
• Deliver architecture/microarchitecture proposals and specifications to the design team
• Collaborate with silicon bring-up and product teams to verify and debug proposals
• Collaborate across teams to bring microarchitectural proposals to fruition

Required qualifications

• BSc, Masters, or PhD in Computer Science/Engineering, or equivalent combination of education, training, and experience
• 8+ years of experience in SOC or ASIC design and architecture
• More than 5 years direct experience in Fabric, System Cache, DRAM controller Architecture or microarchitecture
• Understanding of memory controller architecture, memory scheduling, prioritization and QoS
• Detailed knowledge of ARM bus infrastructure (ACE/AXI/AHB)
• Fluid knowledge of one or more JEDEC standards such as LPDDR, DDR, or HBM
• Background in memory systems and computer architecture

Nice to have

• Experience with BookSim Simulator
• Experience with Platform Architect

Benefits

• Annual bonus eligibility
• Generous benefits

Before you apply

• Must not disclose any trade secrets of a current or previous employer

About the company

The Samsung Research America SOC Architecture Lab provides innovative SoC architecture, bus / memory subsystem, multimedia subsystems and key IP blocks for future Samsung Galaxy products. This lab collaborates with Samsung’s strategic SoC partners, Samsung MX headquarter team, and key R&D teams around the globe.